Network elements such as routers and switches utilize network processors to perform packet processing operations. These network processors are typically implemented in the form of integrated circuits, and include phase-locked loop (PLL) based clock generation circuitry which generates clock signals for the processor core as well as one or more additional clock domains. These additional clock domains may include, for example, domains associated with different types of internal or external memory, such as double data rate (DDR) memory, a host processor domain, and interface domains such as input port clock domains, output port clock domains, etc. It is often desirable to operate the various processor clock domains at different clock rates. For example, the DDR memory domain may operate at a higher clock rate than the processor core. Also, power consumption can often be reduced in a network processor by operating certain domains at clock rates which vary depending upon processing conditions and other factors. Accordingly, the clock generation circuitry is preferably configurable to provide different clock signals to the different domains.
U.S. patent application Ser. No. 11/361,820, filed Feb. 24, 2006 and entitled “Processor with Flexible Clock Configuration,” which is commonly assigned herewith and incorporated by reference herein, discloses improved clock generation techniques for use in network processors and other types of processors, so as to provide greater flexibility in clock configuration while avoiding the need for additional configuration pins or non-volatile memory for storing configuration information.
Despite the considerable advances provided by the techniques described in the above-cited U.S. patent application, a need remains for further improvements in handling multiple clock domains in a network processor or other processor.
For example, with regard to interface domains, it is often the case that a given network processor may be utilized in a number of different processing applications. Each such application may require that the interfaces between the various ports of the network processor and its associated physical layer devices operate at different clock rates. Unfortunately, conventional network processors are unable to provide sufficient flexibility in allocating signal lines of an interface bus to multiple clock domains. One conventional approach simply uses a common clock for all of the ports, which severely restricts functionality. Other conventional approaches involve the use of multiplexed clocks to sample common interface lines. However, this can result in timing disadvantages, such as longer clock insertion delays, and also complicates scan vector testing of the processor.
It is therefore apparent that a need exists for a processor that allows each of a number of different signal lines of an interface bus to belong to one of many clock domains on a configurable basis.